A type of commercially available flash memory product is a MirrorBit® memory device available from Spansion, LLC. A MirrorBit® cell effectively doubles the intrinsic density of a flash memory array by storing two physically distinct bits on opposite sides of a memory cell. Each bit within a cell can be programmed with a binary unit of data (either a logic one or zero) that is mapped directly to the memory array.
An exemplary MirrorBit® memory device 10, illustrated in FIG. 1, includes a P-type semiconductor substrate 12 within which is formed a plurality of spaced-apart source and drain regions 14 and 16, respectively, otherwise known as bit lines. Typically, the substrate 12 has P-type conductivity, and both of the bit lines 14 and 16 have N-type conductivity. A charge trapping layer or stack 18 is disposed on the top surface of the substrate 12 between the bit lines 14 and 16. The charge trapping stack 18 typically comprises, for example, a charge trapping layer, often a silicon nitride layer 20, disposed between a first or bottom silicon dioxide layer (commonly referred to as a tunnel oxide layer) 22 and a second or top silicon dioxide layer 24. A control gate electrode 26, which typically includes an N or N+ polysilicon layer, is formed over the charge trapping stack to form a first storage element or bit 28 and a second storage element or bit 30 of memory cells 32 and 34.
A dual bit memory cell, such as cell 34, is programmed utilizing a procedure known as a hot electron injection technique. More specifically, programming the first bit 28 of the memory cell 34 is performed by injecting electrons into the charge trapping layer 20 and applying a bias between the bit lines 14 and 16 while applying a high voltage to the control gate electrode 26. In an exemplary embodiment, this is accomplished by grounding bit line 16 and applying, for example, approximately 3 to 5 V to bit line 14 and approximately 8 to 10 V to the control gate electrode 26. The voltage on the control gate electrode 26 inverts a channel region 36 while the bias accelerates electrons from bit line 16 into the channel region 36 towards bit line 14. The 4.5 eV to 5 eV kinetic energy gain of the electrons is more than sufficient to surmount the 3.1 eV to 3.5 eV energy barrier at channel region 36/tunnel oxide layer 22 interface and, while the electrons are accelerated towards bit line 16, the field caused by the high voltage on control gate 26 redirects the electrons towards the charge trapping layer 20 in the first bit 28. Those electrons that cross the interface into the charge trapping layer 20 remain trapped for later reading.
Similarly, programming the second bit 30 by hot electron injection into the charge trapping layer 20 is performed by applying a bias between the bit lines 16 and 14 while applying a high voltage to the control gate 26. This may be accomplished by grounding bit line 14 and applying approximately 3 to 5V to bit line 16 and approximately 8 to 10 V to the control gate 26. The voltage on the control gate 26 inverts the channel region 36 while the bias accelerates electrons from bit line 14 into the channel region 36 towards bit line 16. The field caused by the high voltage on control gate 26 redirects the electrons toward the charge trapping layer 20 of second bit 30. Those electrons that cross the channel region 36/tunnel oxide layer 22 into the charge trapping layer 20 remain trapped for later reading.
Advances in semiconductor processing technology often are directed toward increasingly smaller devices, including memory devices. However, as the-above described cells are scaled smaller in size, a transient program disturb phenomenon becomes a challenging obstacle. Transient program disturb results during programming of the dual bit devices. For example, hot holes generated when programming the first bit 28 of an adjacent memory cell 32 have a secondary impact ionization below bit line 16. Freed electrons resulting from the secondary impact ionization tend to diffuse to the disturbed cell 34 below the gate 26, as represented by arrow 40, where they are accelerated by the drain depletion region and injected into the charge trapping stack 18 of both bit 28 and bit 30 of the disturbed cell. This injection of secondary electrons into the charge trapping stack 18 may adversely affect the memory window of the second bit 30.
Accordingly, it is desirable to provide a flash memory device that reduces transient program disturb. In addition, it is desirable to provide a dual bit memory device with dual bit memory cells that can be reliably programmed. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.